This invention relates to a large scale integrated circuit (hereinbelow abbreviated to LSI) and, in particular, to a gate array type LSI.
Among design techniques for LSIs, as those classified to semi-custom LSIs, there are known those of gate array type and those of standard cell type.
As an example of publications, where gate array type LSIs are described, there is e.g. "NIKKEI MICRO-DEVICES" published by Nikkei McGraw Publishing Co., July 1986, p. 111-p. 126.
Fabrication processes of LSIs are divided usually into two processes, i.e. diffusion process and wiring process, and for the gate array type LSIs they are characterized in that the diffusion process remains unchanged (in common), independently of the kind of products, but only the wiring process varies, depending thereon. That is, the diffusion process is common for all kinds of products and is effected so that a plurality of basic cells are arranged in a regular pattern both in the longitudinal and in the transversal direction. On the other hand, the wiring process varies, depending on the kind of products being implemented, and various kinds of wiring are performed, according to user specifications, so as to obtain various kinds of logic LSIs. On the contrary the standard cell type LSIs are fabricated by various independent processes from the step of the diffusion process on the surface of elements.
As stated above, the gate array type has an advantage that the duration of development thereof is shorter than that of the standard cell type, because a part of the fabrication processes is common.
The prior art gate array type LSI will be explained further, referring to FIGS. 3 to 10.
FIG. 3 is a scheme illustrating the construction of a prior art LSI according to the gate array type; FIG. 4 is a scheme showing it more specifically; FIG. 5 is a scheme for explaining an example of the construction of a prior art multilayered wiring; FIG. 6 is a symbolized scheme of a two-input NAND gate; FIG. 7 is an equivalent circuit diagram of the NAND gate indicated in FIG. 6; FIG. 8 illustrates the layout in the case where the NAND gate indicated in FIG. 6 is realized in an element; FIG. 9 is a cross-sectional view of the gate stated above; and FIG. 10 shows an example of the construction of a multilayered wiring according to a prior art technique.
In FIG. 3, reference numeral 1 is a semiconductor substrate; 2 is a basic cell consisting of a pair including a p-type MOS transistor 2a and an n-type MOS transistor 2b; 4 is a certain logic cell composed of basic cells 2; and the region indicated by 5 is a marginal region. In this marginal region 5, the line indicated by a full line 6 in the horizontal direction in the figure is a first layer metal wiring and on the other hand the lines indicated by broken lines 7 belong to a second layer metal wiring. The first layer metal wiring is connected with the second layer metal wiring by interlayer connection through through holes 8.
FIG. 4 illustrates more concretely such a gate array type LSI.
In FIG. 4, in the basic cell 2 described above, a gate electrode wiring 10, which is not shown in FIG. 3, is formed in the vertical direction in the figure between the p-type MOS transistor 2a and the n-type MOS transistor 2b. On the extension of this gate electrode wiring 10 there is formed the marginal region. 5, which has been explained in connection with FIG. 3. A logic cell 4 such as an inverter, a flipflop, etc. can be constructed by one or by combining suitably a plurality of basic cells 2. In order to construct such a logic cell 4, the gate electrode wiring 10 of the basic cell 2, the first and second metal wirings 6, 7 and a through hole 8 are used. Here the through hole 8 is used for connecting the metal wirings belonging to different layers with each other or for connecting electrically the first metal wiring 6 with the p type MOS transistor 2a or the n-type MOS transistor 2b.
FIG. 5 illustrating an example of the construction of a multilayered wiring shows the relation between the construction of wiring paths belonging to different layers and a lattice, which a DA (Design Automation) program can deal with, (hereinbelow called DA lattice). In FIG. 5 the abscissa X indicates the DA lattice point of the wiring perpendicular to the row of the basic cell 2 and the ordinate Y indicates the DA lattice point of the wiring parallel to the row of the basic cell 2, m and n in the coordinates X and Y, respectively, being arbitrary integers.
In FIG. 5 wiring paths 14 indicated by full lines in the vertical direction are wiring paths destined for the gate electrode wiring of the p-type MOS transistor 2a and the n-type MOS transistor 2b, which paths are disposed with a 2-DA lattice interval.
On the other hand wiring paths 15 indicated by full lines in the horizontal direction are wiring paths destined for the first layer metal wiring 6, which paths are disposed with a 1-DA lattice interval in the direction parallel to the row of basic cells.
Further wiring paths 16 indicated by broken lines extending in the vertical direction are wiring paths destined for the second layer metal wiring 7, which paths are disposed parallelly to the wiring paths 14 with a 2-DA lattice interval at positions shifted therefrom by a 1-DA lattice interval.
That is, at the circuit design on the LSI it is possible to realize a desired circuit pattern by using selectively the wiring paths 14, 15 and 16 prepared in advance.
Now the cross-sectional construction of the LSI described above will be briefly explained below. The p-type MOS transistors 2a and n-type MOS transistors 2b are formed in the upper surface portion of the semiconductor substrate 1 by the diffusion process. At first the first layer metal wiring 6 is formed thereon through an insulating layer not shown in the figure. The final product is so constructed that the second layer metal wiring 7 is formed further thereon through another insulating layer.
Hereinbelow the constructional example of the logic cell formed by the basic cell 2 and the metal wirings 6 and 7 will be specifically explained.
The NAND gate as indicated in FIG. 6 is realized in general according to the equivalent circuit indicated in FIG. 7. In FIG. 7, reference numeral 18 is a power source wiring V.sub.DD and 19 is an earth (ground) wiring.
FIG. 8 shows the realization of the equivalent circuit indicated in FIG. 7 by laying out basic cells 2 on the semiconductor substrate.
That is, in FIG. 8, gate electrode wiring 10 on the p-type MOS transistor 2a and the n-type MOS transistor 2b constitutes input terminals A and B and there are disposed the power source wiring 18 and the earth wiring 19 in the direction perpendicular to the gate electrode wiring 10 thereon through an insulating layer.
The inner parts of p-type MOS transistors 2a within the basic cell 2 stated above are connected with each other or with n-type MOS transistors by the first layer metal wiring 6 through the through holes 8. In this way the circuit construction indicated in FIG. 7 is realized.
Further the whole circuit is so constructed that basic cells 2 are separated from each other by isolations 20, as indicated in FIG. 9.
Recently logic cells having a large gate scale have been used more and more often, based on a requirement that a combination of certain logics stored beforehand as a library is used in order to reduce the number of steps in the logic design or on a requirement due to development of automatic design programs, etc.
In the case where such a large scale logic cell is constructed in the gate array type stated above, the internal wirings of the logic cell 4 alone are not enough for the wiring. For this reason, the lead out of wiring from the basic cell 2 could not help but become realized by using necessarily a part of the first layer metal wiring 6 on the marginal region 5, as indicated in FIG. 4.
At this time the second layer metal wiring 7 is used as extension of the wiring in the vertical direction in the figure in order to connect the gate electrode wiring 10 of the basic cell 2 with the first layer metal wiring 6 stated above, as indicated in FIG. 4. As the result, the second layer metal wiring 7 is necessarily used more often, as the gate scale becomes greater.
If the second layer metal wiring 7 is used often for the internal wiring in the logic cell 4, as indicated in FIG. 10, at leading of the wiring between gates only passing on the basic cell 2, the wiring should be disposed, diverted from the portion, where the internal wiring is disposed. As the result, freedom to lead the wiring between gates is reduced.
In this way, if freedom to lead the wiring between gates is reduced, there remain a number of lines between different logic cells, which are not wired, even after execution of an automatic wiring program. Therefore, according to circumstances there was a possibility that additional wiring was difficult even manually. As a result, in a gate array type semiconductor device, such as that according to prior efforts, the gate utilization ratio is reduced and as a result thereof the functions and performance thereof as a semiconductor element become lowered.
Further, as it is clearly seen from FIG. 4, through holes 8 are often used in order to make the second layer metal wiring 7 pass therethrough as extension of wiring to the marginal region 5, which results in complication of the fabrication steps.
In developing the present invention, the inventor considered fully the problems described above and the object thereof of providing a LSI capable of increasing the gate utilization ratio in a gate array type LSI and which has a high reliability.